In processing systems that utilize a plurality of identical pipelines substantially operating in parallel according to a so-called systolic scheme, and to process in parallel data belonging to blocks of data fed in series to the various pipelines, it might be useful or necessary to use a particular timing or clock signals characterized by having active periods alternating with inactive periods. This is commonly defined as windowed clocks, whereby the active period may have a duration different from the period of inactivity. Such requirements occur, for example, in the so-called motion estimators. A motion estimator is a digital processor that calculates an estimate of the motion in a video frame (VF) using a reference frame (RF). Each of the blocks (VF) into which the video frame is normally divided and which for example may be of 16.times.16 pixels (pels), is compared to a correspondent block or with equivalent blocks of the reference frame RF that are within the search area defined by the position of the particular block of the video frame VF. For example, if the dimensions of the search area are 46.times.46 pels, there will be 31.times.31 blocks that the motion estimator will have to compare with the block of the video frame VF. The motion estimator will find the block in the search area that is more similar to the block of the video frame VF and will make available the data that define its position in the search area.
In practice, the motion estimation processor is a machine that must compare many blocks with each other and this means that it would be advantageous to use many processing pipelines (PEs) functioning in parallel. A controller would then coordinate the functions of the different pipelines.
FIG. 1 shows a simplified functional scheme of a motion estimation processor. The systolic array (LINEAR ARRAY OF PE) represents a linear structure of identical processing elements, (PEs), functioning in parallel. The flow of data through the array needs to be controlled by a controller (CONTROLLER). Each PE works in parallel to all the other PEs of the array and the current video block is fed along the array according to a local communication control. The absolute values of the differences between the VF and RF blocks, calculated by the PEs, are stored as distortions in a dedicated accumulator (ACCUMULATOR). The comparators (COMPARATOR) receive representative data of the various distortions in sequence and retain (select) the data relative to the minimum distortion detected. The primary function of the CONTROLLER is that of producing a windowed clock having active phases or periods alternating with inactive phases or periods, for coordinating the functions of the plurality of processing pipelines (PEs) that make up the linear array.
FIG. 2 shows the way a typical windowed clock signal is produced. If f is the clock frequency during active phases, a typical way of producing the windowed clock signal is to start from a clock signal (2f) having twice that frequency. The 2f frequency can be divided by two through a common digital divider thus obtaining an f frequency signal, and by a larger multiple of two (in the example by 16), thus obtaining an f/16 frequency signal. These two derived clock signals of fractional frequency in respect to the frequency 2f of the starting signal, obtained by digital frequency division, are supplied to an AND gate to produce the required windowed clock signal that represents the logic product of the two derived clocks, as diagrammatically illustrated in FIG. 2.
The delay introduced by the combinatory logic AND circuit can be, as it is well known, eliminated by using a D-latch circuit, to which the 2f frequency signal may be fed as the sampling clock signal. The disadvantage of this method is represented by requiring a 2f frequency primary signal that is twice the clock frequency actually required during the active phases of the windowed clock signal to be produced. For example in a typical application of a motion estimate system, the requisite of having a windowed clock signal with a frequency, during the active phases, of 72 MHz would require the availability of a master clock signal with twice that frequency, that is of 144 MHz. Clearly, this aspect may be extremely burdensome because it may impose severe constraints to the hardware architecture and to the components used.